"It was a wonderful experience interacting with you and appreciate the way you have planned and executed the whole publication process within the agreed timelines.”
Subrat SaurabhAuthor of Kuch Woh Pal
If you can spare half an hour, then we can guarantee success at your next VLSI (Very Large Scale Integration)-FPGA (Field Programmable Gate Array)-STA (Static Timing analysis) interview. Do you want to secure at least 3 to 4 job offers by succeeding at all the phone and on-site job interviews for the FPGA DESIGN ENGINEER position? Or do you simply want answers for the most frequently asked interview questions in VLSI-FPGA digital circuit design?
Did you know that people who target question-answer type preparation for a job interview are 3-4 times more likely to get a job offer than those who don't? Did you also know that there is a set of questions that is likely to be repeatedly asked by interviewers across the industry, no matter who you talk with in the VLSI-FPGA digital design?
After a total of 17 unsuccessful interviews, we thought of writing a book to help upcoming undergrads and experience professionals to get selected in such interviews. The book covers every dimension related to FPGA, Verilog, STA and Protocols.
In simple words, don’t search anything on the internet, this book is the Google of FPGA and Verilog.
Bharat Agarwal, Kshitij Goel
Bharat Agarwal: He currently works as a Project Scientist in the Electrical Department in IIT, Delhi. Bharat has 4 years of experience in the field of FPGA, Verilog, MATLAB and STA. He completed his UG from Galgotias University in 2016. After that he worked for some giants of the field of FPGA like Saankhya Labs and Mahindra Telephonics Integrated System.
Kshitij Goel: He currently works as a FPGA Design Engineer in Pretlist India Private Limited. Kshitij has more than 5 years of experience in the field of FPGA, VHDL, Verilog, MATLAB, Simulink, XILINX System Generator. He completed his under graduation from UPTU in 2014. After completing graduation, he has worked for the Indian Navy R&D Organization and works on the Physical Layer Design of Software Defined Radio in the FPGA for more than 3 years and then worked in the Arrow Electronics
