"It was a wonderful experience interacting with you and appreciate the way you have planned and executed the whole publication process within the agreed timelines.”
Subrat SaurabhAuthor of Kuch Woh Pal
Book Contain of Introduction to Verilog HDL: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Programming Language Interface, Module. Language Constructs and Conventions: Introduction, Keywords, Identifiers, White Space, Characters, Comments, Numbers, Strings, Logic Values, Data Types, Scalars and Vectors, Operators. Gate Level Modeling: Introduction, AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, Tristate Gates, Array of Instances of Primitives, Design of Flip-Flops with Gate Primitives, Gate Delay, Strengths and Contention Resolution, Net Types.
Prof. Vishwajit K. Barbudhe
Prof. V. K. Barbudhe working as Professor at Jagadambha college of Engineering and Technology for UG and PG Department of Electronics and Telecommunication Engineering . Total Years of Experience 11+ . He publish more than 50+ Papers in International Journals . He work as International Expert at International Conferences . He worked as a Editorial Board Members in 15+ International Journals and Reviewer in 100+ International Journals and International Conferences . Project Guided 10+ PG students and 50+ UG Students . He publish more than 140+ Books on Electronics and Computer Engineering Subject.
