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VLSI Design Laboratory Manual is intended for undergraduate students of engineering. It covers design entry and simulation of combinational and sequential logic circuits using verilog HDL in Xilinx ISE and Simulation through Schematic entry in SPICE.
The manual includes simulation of Digital Logic gates, Adders, Subtractors, Multiplexers, Demultiplexers, 8 bit parallel adder/subtractor, 4 bit Multiplier, Encoder and Decoder, Flip-flops, and CMOS circuit design using SPICE.
Dr. R. Lavanya, Dr. K. Sheela Sobana Rani, Ms. R. Gayathri, Dr. R. Jaikumar
Dr.R.Lavanya is currently working as an Assistant Professor (Senior Grade) at Sri Ramakrishna Institute of Technology,Coimbatore in the Department of ECE. She has over 10 years of teaching experience. Her research interests include VLSI, IoT and Hardware security. .
Dr.K.Sheela Sobana Rani has over 15 years of teaching experience. She is currently working as an Associate Professor in EEE Department of Sri Ramakrishna Institute of Technology, Coimbatore. Her research interest includes Wireless communication, Wireless networks and VLSI.
Ms.R.Gayathri has 7 years of Teaching experience. She is working as an Assistant Professor (Senior Grade) in ECE Department of Sri Ramakrishna Institute of Technology, Coimbatore and currently pursuing her Ph.D. under Anna University Chennai. Her fields of interest are Wireless Communication, Wireless Networks and Digital System Design.
Dr.R.Jaikumar has over 11 years of teaching experience and is presently working as an Associate Professor at KGISL Institute of Technology, Coimbatore. His research interests include VLSI design, Industrial automation and Embedded systems.
